1. Technical Field
This disclosure relates to integrated circuits, and more particularly to transistor sizing.
2. Description of the Related Art
Integrated circuit designers use libraries that include the devices that will be used during the design of the integrated circuit. More particularly, once the circuit has been logically proven, the design is then synthesized according to the particular manufacturing facility and technology that will be used. The technology typically refers to the minimum transistor sizes (e.g., channel length and width) that the facility can reliably manufacture. It is generally considered advantageous to make devices as small as possible (i.e., scaling) since more devices may be fit onto an integrated circuit, and thus more integrated circuit die may fit onto a wafer, which reduces the cost of making the integrated circuit. In addition, as devices scale, the switching speed of the devices also generally decreases.
However, although there are advantages to manufacturing devices at the smallest possible size that a given technology will support, in some cases there may be drawbacks. For example, narrow width effects have been observed in integrated circuits for quite some time. As device geometries have continued their downward trend these effects have become more prominent. One notable effect is that as the channel width decreases well below 0.4 microns, and certainly below 100 nm, the threshold voltage (Vt) sharply increases even in devices that employ shallow trench insulator (STI) technology. For devices that will be used at an operating voltage that is well above the Vt, this may not be an issue. However, along with decreases in device size, has been a reduction in the operating voltage. Accordingly, as the operating voltage decreases and Vt increases, at some point the increase in Vt becomes too large for a given operating voltage and the device may be difficult to turn on or to operate reliably. This may be especially problematic in view of device variability due to process, voltage, and temperature (PVT) variations across an integrated circuit die or wafer.